provide a measure of protection from crack initiation and growth. Therefore, for different devices, it is important to understand the magnitude of residual stresses near etched features and to be able to control the state of residual stress during processing. Methods to control residual stresses and wafer bow include utilizing different glass chemistries [5,6] post bond annealing steps [8] and current-limited anodic bonding [10]. However, each of these approaches is restricted by other processing requirements, additional processing times, or a limited effect. As such, no simple approach for residual stress control in anodic bonded devices has been devised. The purpose of this presentation is to describe a simple modification to the standard bonding process as a method to control the residual stress in anodically bonded samples. Furthermore, post bond wafer bow generated by these residual stresses are compared to numerical predictions from a ABAQUS finite element model accounting for the nonlinear coefficients of thermal expansion of the bonded substrates. II. EXPERIMENTAL PROCEDURES The anodic bonding process utilized in these experiments joins a 100 mm single crystal, double-side polished silicon wafer and a 100 mm borosilicate glass wafer, in our case a Pyrex 7740 wafer. For some samples, circular and square features were etched into the silicon wafer to study stress concentrating effects of these geometry, specifically to investigate effects of corner radii as well as feature orientation, size and proximity. Feature in-plane diameters are in the range of 250-1000 µm while the depths were typically near 100 µm. To pattern the interfacial features in virgin silicon wafer a positive photoresist is spun prior to being exposed through the photomask. After developing the photoresist, the silicon etching process is completed in an ICP-DRIE etching system using the Bosch process. The Bosch process combines an etching step using accelerated Ar+ ions to etch the exposed silicon surface with an inhibiting step that produces vertical sidewalls [11]. Standard RCA-1 and RCA-2 cleans are performed on the patterned silicon wafers to remove any remaining organic materials or heavy metals [11]. To reduce surface roughening, a diluted RCA-1 solution of deionized water, hydrogen peroxide and ammonium hydroxide at a ratio of 5:1:0.1 is prepared. Immediately after the RCA1 clean, the wafer is placed in an RCA-2 solution of deionized water, hydrogen peroxide and hydrogen chloride at a ratio of 5:1:1. The Pyrex wafer is cleaned with a Piranha solution, with a 5:1 mixture of sulfuric acid and hydrogen peroxide. The wafers are bonded in an Electronic Visions Group (EVG) 501 vacuum bonding system. For these samples, anodic bonding takes place in a vacuum better than 2x10-4 mbar. For isothermal bonding protocols, the bond chuck temperatures are set to 400°C. As a means of comparison, an anisothermal bonding protocol is used to provide roughly opposite curvature by bonding at silicon temperatures of 388°C and Pyrex at temperatures of 343°C. Upon reaching temperature, pressure is applied to bring the centers of the wafers into contact and a voltage of 400V is maintained for 25 minutes to ensure the bonding process is complete. To verify the magnitude of bulk stresses in bonded wafer pairs, an Alpha Step IQ Surface Profiler is used to scan 1000 samples at 25 mm from the wafer center. It is assumed that the bulk curvature of the substrate is represented by the local curvature over these sections. The measurements are averaged to estimate the wafer bow after bonding. Residual stress concentrations at etched features are quantified using an infrared photoelastic stress analysis system known as the IR-GFP [13]. Most of images shown here are taken with a 5X optical magnification that provides a spatial viewing window of approximately 1.78 mm x 1.33 mm with a spatial resolution of 1.3 µm. This magnification allows for a sufficient viewing area for any feature in the silicon. A through thickness spatially resolved value of the shear stress cannot currently be obtained using the IR-GFP with this geometry, since the shear stress measurement is integrated through the entire sample thickness, including both the glass and the silicon wafers. A comprehensive modeling framework is being developed to relate the retardation of the elliptically polarized light to in-plane shear stress. The data presented here are in terms of ellipticity or “intensity” of depolarization, and are directly related to residual shear stress. III. RESULTS AND DISCUSSION The surface profile line scans from the isothermal and anisothermal bonded wafers are shown in Figure 1, showing the wafer bow that resulted from each bond recipe. The isothermal wafer protocol resulted in a wafer µm sections of the wafer surfaces. The profilometer obtains curvature measurements of the bonded 270
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