210 M. J. Szydlowski et al. Fig. 19.1 System architecture system (DAQ). Four main types of nodes are proposed: (i) a control node (master) responsible for synchronisation, control of basic actuators (motors, pumps) and basic health monitoring of the system; (ii) excitation nodes that are multichannel signal generators driving various exciters at multiple frequencies; (iii) acquisition nodes that allow multichannel data capture with different sampling rates, reconfigurable data reduction and processing capabilities; (iv) storage nodes and processing nodes that provide additional processing resources as well as serve as a long-term data storage. Figure 19.1 depicts such a simple network consisting of a master node, N acquisition nodes and a storage node. All nodes of the network are synchronised using a distributed hardware clock and trigger system, ensuring minimal phase misalignment between the acquired signals. 19.3 Node Architecture Each of the nodes share the same basic architecture in order to be part of the network. Depending on the specialty of the node different functionalities are either added or disabled. Figure 19.2 presents the overall node architecture. Each node has three main layers, (i) a software layer that uses a real-time operating system (RTOS), (ii) a hardware layer using FPGA (Field Programable Gate Array) and (iii) a storage layer. The first two layers thereby have direct access to the on-board memory (DMA) and are capable of sharing and processing the data in it. The hardware layer is responsible for signal acquisition and signal output (if required). It controls the analogue to digital (ADC), digital to analogue (DAC), and fast digital inputs and outputs (DI/DO). It also ensures continuous node synchronization (SYNC module) and it can be used to apply a series of data pre-processing and reduction steps thanks to the FPGA (Field Programmable Gate Arrays) capability. The node sampling synchronization is implemented via hardware triggers (TRIG) and PLL (Phase Lock Loop) clocks with the master clock (CLK) running at 13 MHz. Due to the hardware implementation, pre-processing the data can be handled on the fly, leading to a significant reduction of what needs to be passed to the software layer via DMA (Direct Memory Access). The software part of each node is built in a RTOS (Real Time Operating System) to increase the speed and computational costs and ensure fast reaction time of the system. The heart of the software layer is the control module (CTRL) responsible of the systems operation. The built-in software enables further data processing (compression, scaling) which goes beyond the limits of the hardware layer. The processing is done in circular buffer with a fixed number of samples. This layer gives also access to the user interface (UI) in order to set up and provide information about the test progress. The CTRL module and Watchdog module ensure that the overall network and the node is operational and running as expected. The communication is
RkJQdWJsaXNoZXIy MTMzNzEzMQ==